TMS320VC5441AZGU

DSP Fixed-Point 16Bit 133MHz 532MIPS 169Pin BGA MICROSTAR

Introduction

This section describes the main features of the TMS320VC5441 digital signal processor DSP, lists the pin assignments, and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.

Description

The TMS320VC5441 fixed-point digital signal processor is a quad-core solution running at 532-MIPS performance. The 5441 consists of four DSP subsystems with shared program memory. Each subsystem consists of one TMS320C54x DSP core, 32K-word program/data DARAM, 64K-word data DARAM, three multichannel buffered serial ports, DMA logic, one watchdog timer, one general-purpose timer, and other miscellaneous circuitry.

TMS320VC5441 Features

• 532-MIPS Quad-Core DSP Consisting of Four Independent Subsystems

• Each Core has an Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Bus

• 40-Bit Arithmetic Logic Unit ALU Including a 40-Bit Barrel-Shifter and Two 40-Bit Accumulators Per Core

• Each Core has a 17-Bit × 17-Bit Parallel Multiplier Coupled to a 40-Bit Adder for Non-Pipelined Single-Cycle Multiply/Accumulate MAC Operations

• Each Core has a Compare, Select, and Store Unit CSSU for the Add/Compare Selection of the Viterbi Operator

• Each Core has an Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle

• Each Core has Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units ARAUs

• Total 640K-Word × 16-Bit Dual-Access On-Chip RAM 256K-Word x 16-Bit Shared Memory and 96K-Word x 16-Bit Local Memory Per Subsystem

• Single-Instruction Repeat and Block-Repeat Operations

• Instructions With 32-Bit Long Word Operands

• Instructions With 2 or 3 Operand Reads

• Fast Return From Interrupts

• Arithmetic Instructions With Parallel Store and Parallel Load

• Conditional Store Instructions

• Output Control of CLKOUT

• Output Control of Timer Output TOUT

• Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions

• Dual 1.6-V Core and 3.3-V I/O Power Supplies for Low-Power, Fast Operations

• 7.5-ns Single-Cycle Fixed-Point Instruction

• Twenty-Four Channels of Direct Memory Access DMA for Data Transfers With No CPU Loading Six Channels Per Subsystem

• Twelve Multichannel Buffered Serial Ports McBSPs, Each With 128-Channel Selection Capability Three McBSPs per Subsystem

• 16-Bit Host-Port Interface HPI

• Software-Programmable Phase-Locked Loop PLL Provides Several Clocking Options Requires External TTL Oscillator

• On-Chip Scan-Based Emulation Logic, IEEE Standard 1149.1 JTAG Boundary Scan Logic

• Four Software-Programmable Timers One Per Subsystem

• Four Software-Programmable Watchdog Timers One Per Subsystem

• Sixteen General-Purpose I/Os Four Per Subsystem

• Provided in 176-pin Plastic Low-Profile Quad Flatpack LQFP Package PGF Suffix

• Provided in 169-ball MicroStar BGA™ Package GGU Suffix