CD74HCT646M96

八路总线收发器和寄存器具有三态输出 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock CLKAB or CLKBA input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices.

Output-enable OE\\\\ and direction-control DIR inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers.

The select-control SAB and SBA inputs can multiplex stored and real-time transparent mode data. DIR determines which bus receives data when OE\ is active low. In the isolation mode OE\ high, A data can be stored in one register and/or B data can be stored in the other register.

When an output function is disabled, the input function still is enabled and can be used to store data. Only one of the two buses, A or B, can be driven at a time.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.