1线路至10线路时钟驱动器，具有三态输出 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS
The CDC351 is a high-performance clock-driver circuit that distributes one input A to ten outputs Y with minimum skew for clock distribution. The output-enable OE\ input disables the outputs to a high-impedance state. The CDC351 operates at nominal 3.3-V VCC.
The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.