PEF20532

2通道串行优化的通信控制器 2 Channel Serial Optimized Communication Controller

Introduction

The SEROCCO-M is a Serial Communication Controller with two independent serial channels1. The serial channels are derived from updated protocol logic of the ESCC and DSCC4 device family providing a large set of protocol support and variety in serial interface configuration. This allows easy integration to different environments and applications.

Features

Serial communication controllers SCCs

• Two independent channels

• Full duplex data rates on each channel of up to 16 Mbit/s sync - 2 Mbit/s with DPLL

• 64 Bytes deep receive FIFO per SCC

• 64 Bytes deep transmit FIFO per SCC

Serial Interface

• On-chip clock generation or external clock sources

• On-chip DPLLs for clock recovery

• Baud rate generator

• Clock gating signals

• Clock gapping capability

• Programmable time-slot capability for connection to TDM interfaces e.g. T1, E1

• NRZ, NRZI, FM and Manchester data encoding

• Optional data flow control using modem control lines RTS, CTS, CD

• Support of bus configuration by collision detection and resolution

Bit Processor Functions

• HDLC/SDLC Protocol Modes

   – Automatic flag detection and transmission

   – Shared opening and closing flag

   – Generation of interframe-time fill ’1’s or flags

   – Detection of receive line status

   – Zero bit insertion and deletion

   – CRC generation and checking CRC-CCITT or CRC-32

   – Transparent CRC option per channel and/or per frame

   – Programmable Preamble 8 bit with selectable repetition rate

   – Error detection abort, long frame, CRC error, short frames

• Bit Synchronous PPP Mode

   – Bit oriented transmission of HDLC frame flag, data, CRC, flag

   – Zero bit insertion/deletion

– 15 consecutive ’1’ bits abort sequence

• Octet Synchronous PPP Mode

   – Octet oriented transmission of HDLC frame flag, data, CRC, flag

   – Programmable character map of 32 hard-wired characters 00H-1FH

   – Four programmable characters for additional mapping

   – Insertion/deletion of control-escape character 7DH for mapped characters

• Asynchronous PPP Mode

   – Character oriented transmission of HDLC frame flag, data, CRC, flag

   – Start/stop bit framing of single character

   – Programmable character map of 32 hard-wired characters 00H-1FH

   – Four programmable characters for additional mapping

   – Insertion/deletion of control-escape character 7DH for mapped characters

• Asynchronous ASYNC Protocol Mode

   – Selectable character length 5 to 8 bits

   – Even, odd, forced or no parity generation/checking

   – 1 or 2 stop bits

   – Break detection/generation

   – In-band flow control by XON/XOFF

   – Immediate character insertion

   – Termination character detection for end of block identification

   – Time out detection

   – Error detection parity error, framing error

• BISYNC Protocol Mode

   – Programmable 6/8 bit SYN pattern MONOSYNC

   – Programmable 12/16 bit SYN pattern BISYNC

   – Selectable character length 5 to 8 bits

   – Even, odd, forced or no parity generation/checking

   – Generation of interframe-time fill ’1’s or SYN characters

   – CRC generation CRC-16 or CRC-CCITT

   – Transparent CRC option per channel and/or per frame

   – Programmable Preamble 8 bit with selectable repetition rate

   – Termination character detection for end of block identification

   – Error detection parity error, framing error

• Extended Transparent Mode

   – Fully bit transparent no framing, no bit manipulation

   – Octet-aligned transmission and reception

• Protocol and Mode Independent

   – Data bit inversion

   – Data overflow and underrun detection

   – Timer

  

Protocol Support

• Address Recognition Modes

   – No address recognition Address Mode 0

   – 8-bit high byte address recognition Address Mode 1

   – 8-bit low byte or 16-bit high and low byte address recognition Address Mode 2

• HDLC Automode

   – 8-bit or 16-bit address generation/recognition

   – Support of LAPB/LAPD

   – Automatic handling of S- and I-frames

   – Automatic processing of control bytes

   – Modulo-8 or modulo-128 operation

   – Programmable time-out and retry conditions

   – SDLC Normal Response Mode NRM operation for slave

• Signaling System #7 SS7 support

   – Detection of FISUs, MSUs and LSSUs

   – Unchanged Fill-In Signaling Units FISUs not forwarded

   – Automatic generation of FISUs in transmit direction incl. sequence number

   – Counting of errored signaling units

• Optional DTACK/READY controlled cycles

Microprocessor Interface

• 8/16-bit bus interface

• Multiplexed and De-multiplexed address/data bus

• Intel/Motorola style

• Asynchronous interface

• Maskable interrupts for each channel