S912ZVMC12F1MKH

NXP  S912ZVMC12F1MKH  芯片, 微控制器, 16位, S12 MAGNIV, 25MHZ

The is a MagniV mixed signal S12ZVM-family 16-bit Microcontroller using the NVM + UHV technology that offers the capability to integrate 40V analog components. This family reuses many features from the existing S12/S12X portfolio. The particular differentiating features of this family are the enhanced S12Z core, the combination of dual-ADC synchronized with PWM generation and the integration of "high-voltage" analog modules, including the voltage regulator, Gate Drive Unit and either Local Interconnect Network physical layer or CAN Physical layer. The MC9S12ZVM-Family includes error correction code ECC on RAM and flash memory, EEPROM for diagnostic or data storage, a fast analog-to-digital converter ADC and a frequency modulated phase locked loop IPLL that improves the EMC performance. The MC9S12ZVM-Family allows the integration of several key system components into a single device, optimizing system architecture and achieving significant space savings.

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Harvard architecture - parallel data and code access

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3-Stage pipeline

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32-bit Wide instruction and data bus

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32-bit ALU

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24-bit Addressing 16MB linear address space

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Phase locked loop IPLL frequency multiplier with internal filter

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1MHz Internal RC oscillator with +/-1.3% accuracy

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4-20MHz Amplitude controlled pierce oscillator

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Internal COP watchdog module

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6-channel, 15-bit pulse width modulator with fault protection PMF

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Low side and high side FET pre-drivers for each phase

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2 Parallel ADC with 12-bit resolution

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Programmable trigger unit PTU for synchronization of PMF and ADC

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Serial peripheral interface SPI module

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SCI module with interface to internal LIN physical layer transceiver

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Additional SCI not connected to LIN physical layer

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4-channel Timer module TIM0 with input capture/output compare

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MSCAN 1Mbps, CAN 2.0 A, B software compatible module

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On-chip voltage regulator VREG

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2 Current sense circuits for overcurrent detection or torque measurement