KIT33903BD5EVBE

NXP KIT33903BD5EVBE Evaluation Kit for MC33903BD5 System Basis Chip Gen2 with CAN High Speed and LIN Interface

The is a 33903BD5, SBC Gen2 with CAN high speed and LIN interface evaluation board. This evaluation board includes one I/O test point that can be configured to be pulled up to VSUP or pulled down to GND through a resistor and indicator LED. It is easily configured via jumper settings. The SBC can also be exercised in debug mode watchdog re-fresh/monitoring not needed by simply populating a jumper. Specified resistor pull-downs can be implemented on the DBG and MUX pins via simple jumper configurations. The status of I/O-0, 5V_CAN, SAFE, and VDD can be visually monitored via on-board LEDs. The CAN and LIN Bus signals are provided through terminal block connectors. An isolated terminal block connector is implemented to provide power to the evaluation board with an external DC power supply.

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Nominal operating supply voltage range of 5.5V to 27V

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5V/3.3V regulator for the MCU with an external PNP ballast transistor to increase current capability

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Multiple CAN Bus termination options supported via socket

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One high/low side I/O SPI configurable accessible through a test point

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Status of I/O-0 indicated by LED dependent on jumper configuration

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Debug mode/watchdog configuration via jumper settings

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MUX output voltage accessible through a test point and external resistor selectable through a jumper

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I_WAKE_I test point to enable a FET and load VDD with current to wake up the SBC

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LIN1_T and LIN2_T test points to monitor I/O voltages SPI configurable

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100 mil 2x8 pin standard header connector for SPI communication