CD54ACT161

具有异步复位的同步可预设的二进制计数器

The ’ACT161 devices are 4-bit binary counters. These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable ENP, ENT inputs and internal gating. This mode of operation eliminates the output counting spikes that normally are associated with synchronous ripple-clock counters. A buffered clock CLK input triggers the four flip-flops on the rising positive-going edge of the clock waveform.

These devices are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function is asynchronous. A low level at the clear CLR\ input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load LOAD\, or enable inputs.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output RCO. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum 9 or 15 with QA high. This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.

The counters feature a fully independent clock circuit. Changes at control inputs ENP, ENT, or LOAD\\ that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter whether enabled, disabled, loading, or counting is dictated solely by the conditions meeting the stable setup and hold times.

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Inputs Are TTL-Voltage Compatible

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Internal Look-Ahead for Fast Counting

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Carry Output for n-Bit Cascading

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Synchronous Counting

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Synchronously Programmable

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SCR-Latchup-Resistant CMOS Process and Circuit Design

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Exceeds 2-kV ESD Protection per MIL-STD-883, Method 3015