MC74VHCT139A

双路2至4解码器/多路解复用器 Dual 2−to−4 Decoder/ Demultiplexer

The is an advanced high speed CMOS 2-to-4 decoder/ demultiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. When the device is enabled Ebar = low, it can be used for gating or as a data input for demultiplexing operations. When the enable input is held high, all four outputs are fixed high, independent of other inputs. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device output is compatible with TTL-type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic-level translator from 3.0 V CMOS logic to 5.0 V CMOS logic, or from 1.8 V CMOS logic to 3.0 V CMOS logic while operating at the high-voltage power supply. The MC74VHCT139A input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHCT139A to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when V = 0 V. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot insertion, etc.

Features

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High Speed: tPD = 5.0ns Typ at VCC = 5V

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Low Power Dissipation: ICC = 4mA Max at TA = 25°C

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TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V

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Power Down Protection Provided on Inputs and Outputs

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Balanced Propagation Delays

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Designed for 2V to 5.5V Operating Range

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Low Noise: VOLP = 0.8 V Max

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Pin and Function Compatible with Other Standard Logic Families

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Latchup Performance Exceeds 300mA

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ESD Performance: HBM > 2000V; Machine Model > 200V

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Chip Complexity: 100 FETs or 25 Equivalent Gates

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Pb-Free Packages are Available*