74F676SC

16Bit Serial/Parallel-In, Serial-Out Shift Register

General Description

The ’F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode M input is HIGH, information present on the parallel data P0–P15 inputs is entered on the falling edge of the Clock Pulse CP input signal. When M is LOW, data is shifted out of the most significant bit position while information present on the Serial SI input shifts into the least significant bit position. A HIGH signal on the Chip Select CS input prevents both parallel and serial operations.

Features

■ 16-bit parallel-to-serial conversion

■ 16-bit serial-in, serial-out

■ Chip select control

■ Slim 24 lead 300 mil package