OMAP3530

应用处理器

and OMAP3525 devices are based on the enhanced OMAP 3 architecture.

The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

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Streaming video

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Video conferencing

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High-resolution still image

The device supports high-level operating systems HLOSs, such as:

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Linux®

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Windows® CE

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Android™

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

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Microprocessor unit MPU subsystem based on the ARM Cortex-A8 microprocessor

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IVA2.2 subsystem with a C64x+ digital signal processor DSP core

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PowerVR SGX subsystem for 3D graphics acceleration to support display OMAP3530 device only

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Camera image signal processor ISP that supports multiple formats and interfacing options connected to a wide variety of image sensors

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Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC and PAL video out.

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Level 3 L3 and level 4 L4 interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

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A comprehensive power- and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption.

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Memory-stacking feature using the package-on-package POP implementation CBB and CBC packages only

OMAP3530 and OMAP3525 devices are available in a 515-pin s-PBGA package CBB suffix, 515-pin s-PBGA package CBC suffix, and a 423-pin s-PBGA package CUS suffix. Some features of the CBB and CBC packages are not available in the CUS package. See Table 1-1 for package differences.

This data manual presents the electrical and mechanical specifications for the OMAP3530 and OMAP3525 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP3530 and OMAP3525 applications processors unless otherwise indicated. This data manual consists of the following sections:

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Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description

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Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics

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Section 4: Clock Specifications input and output clocks, DPLL and DLL

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Section 5: Video Dac Specifications

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Section 6: Timing Requirements and Switching Characteristics

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Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging

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OMAP3530 and OMAP3525 Devices:

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OMAP™ 3 Architecture

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MPU Subsystem

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Up to 720-MHz ARM® Cortex™-A8 Core

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NEON™ SIMD Coprocessor

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High-Performance Image, Video, Audio IVA2.2™ Accelerator Subsystem

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Up to 520-MHz TMS320C64x+™ DSP Core

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Enhanced Direct Memory Access EDMA Controller 128 Independent Channels

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Video Hardware Accelerators

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PowerVR® SGX™ Graphics Accelerator OMAP3530 Device Only

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Tile-Based Architecture Delivering up to 10 MPoly/sec

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Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality

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Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0

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Fine-Grained Task Switching, Load Balancing, and Power Management

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Programmable High-Quality Image Anti-Aliasing

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Fully Software-Compatible with C64x and ARM9™

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Commercial and Extended Temperature Grades

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Advanced Very-Long-Instruction-Word VLIW TMS320C64x+ DSP Core

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Eight Highly Independent Functional Units

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Six ALUs 32- and 40-Bit, Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle

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Two Multipliers Support Four 16 x 16-Bit Multiplies 32-Bit Results per Clock Cycle or Eight 8 x 8-Bit Multiplies 16-Bit Results per Clock Cycle

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Load-Store Architecture with Nonaligned Support

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64 32-Bit General-Purpose Registers

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Instruction Packing Reduces Code Size

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All Instructions Conditional

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Additional C64x+ Enhancements

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Protected Mode Operation

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Exceptions Support for Error Detection and Program Redirection

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Hardware Support for Modulo Loop Operation

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C64x+ L1 and L2 Memory Architecture

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32KB of L1P Program RAM and Cache Direct Mapped

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80KB of L1D Data RAM and Cache 2-Way Set-Associative

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64KB of L2 Unified Mapped RAM and Cache 4-Way Set-Associative

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32KB of L2 Shared SRAM and 16KB of L2 ROM

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C64x+ Instruction Set Features

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Byte-Addressable 8-, 16-, 32-, and 64-Bit Data

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8-Bit Overflow Protection

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Bit Field Extract, Set, Clear

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Normalization, Saturation, Bit-Counting

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Compact 16-Bit Instructions

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Additional Instructions to Support Complex Multiplies

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ARM Cortex-A8 Core

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ARMv7 Architecture

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TrustZone®

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Thumb®-2

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MMU Enhancements

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In-Order, Dual-Issue, Superscalar Microprocessor Core

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NEON Multimedia Architecture

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Over 2x Performance of ARMv6 SIMD

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Supports Both Integer and Floating-Point SIMD

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Jazelle® RCT Execution Environment Architecture

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Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack

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Embedded Trace Macrocell ETM Support for Noninvasive Debug

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ARM Cortex-A8 Memory Architecture:

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16-KB Instruction Cache 4-Way Set-Associative

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16-KB Data Cache 4-Way Set-Associative

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256-KB L2 Cache

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112KB of ROM

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64KB of Shared SRAM

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Endianess:

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ARM Instructions – Little Endian

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ARM Data – Configurable

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DSP Instruction and Data - Little Endian

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External Memory Interfaces:

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SDRAM Controller SDRC

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16- and 32-Bit Memory Controller with 1GB of Total Address Space

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Interfaces to Low-Power Double Data Rate LPDDR SDRAM

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SDRAM Memory Scheduler SMS and Rotation Engine

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General Purpose Memory Controller GPMC

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16-Bit-Wide Multiplexed Address and Data Bus

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Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin

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Glueless Interface to NOR Flash, NAND Flash with ECC Hamming Code Calculation, SRAM, and Pseudo-SRAM

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Flexible Asynchronous Protocol Control for Interface to Custom Logic FPGA, CPLD, ASICs, and so forth

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Nonmultiplexed Address and Data Mode Limited 2-KB Address Space

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System Direct Memory Access sDMA Controller 32 Logical Channels with Configurable Priority

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Camera Image Signal Processor ISP

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CCD and CMOS Imager Interface

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Memory Data Input

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BT.601 8-Bit and BT.656 10-Bit Digital YCbCr 4:2:2 Interface

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Glueless Interface to Common Video Decoders

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Resize Engine

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Resize Images From 1/4x to 4x

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Separate Horizontal and Vertical Control

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Display Subsystem

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Parallel Digital Output

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Up to 24-Bit RGB

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HD Maximum Resolution

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Supports Up to 2 LCD Panels

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Support for Remote Frame Buffer Interface RFBI LCD Panels

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2 10-Bit Digital-to-Analog Converters DACs Supporting:

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Composite NTSC and PAL Video

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Luma and Chroma Separate Video S-Video

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Rotation 90-, 180-, and 270-Degrees

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Resize Images From 1/4x to 8x

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Color Space Converter

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8-Bit Alpha Blending

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Serial Communication

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5 Multichannel Buffered Serial Ports McBSPs

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512-Byte Transmit and Receive Buffer McBSP1, McBSP3, McBSP4, and McBSP5

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5-KB Transmit and Receive Buffer McBSP2

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SIDETONE Core Support McBSP2 and McBSP3 Only For Filter, Gain, and Mix Operations

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Direct Interface to I2S and PCM Device and TDM Buses

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128-Channel Transmit and Receive Mode

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Four Master or Slave Multichannel Serial Port Interface McSPI Ports

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High-, Full-, and Low-Speed USB OTG Subsystem 12- and 8-Pin ULPI Interface

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High-, Full-, and Low-Speed Multiport USB Host Subsystem

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12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface

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Supports Transceiverless Link Logic TLL

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One HDQ™/1-Wire® Interface

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Three UARTs One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes

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Three Master and Slave High-Speed Inter-Integrated Circuit I2C Controllers

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Removable Media Interfaces:

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Three Multimedia Card MMC/Secure Digital SD with Secure Data I/O SDIO

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Comprehensive Power, Reset, and Clock Management

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SmartReflex™ Technology

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Dynamic Voltage and Frequency Scaling DVFS

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Test Interfaces

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IEEE 1149.1 JTAG Boundary-Scan Compatible

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ETM Interface

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Serial Data Transport Interface SD

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12 32-Bit General-Purpose Timers

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2 32-Bit Watchdog Timers

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1 32-Bit 32-kHz Sync Timer

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Up to 188 General-Purpose I/O GPIO Pins Multiplexed with Other Device Functions

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65-nm CMOS Technologies

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Package-On-Package POP Implementation for Memory Stacking Not Available in CUS Package

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Discrete Memory Interface Not Available in CBC Package

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Packages:

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515-pin s-PBGA Package CBB Suffix,

.5-mm Ball Pitch Top, .4-mm Ball Pitch Bottom

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515-pin s-PBGA Package CBC Suffix,

.65-mm Ball Pitch Top, .5-mm Ball Pitch Bottom

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423-pin s-PBGA Package CUS Suffix,

.65-mm Ball Pitch

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1.8-V I/O and 3.0-V MMC1 Only,

0.985-V to 1.35-V Adaptive Processor Core Voltage

0.985-V to 1.35-V Adaptive Core Logic Voltage

**Note**: These are default Operating Performance Point OPP voltages and could be optimized to lower values using SmartReflex AVS.