SN74LS165AN

TEXAS INSTRUMENTS  SN74LS165AN  移位寄存器, LS系列, 并行至串行、串行至串行, 1元件, DIP, 16 引脚, 4.75 V, 5.25 V

The is a 8-bit parallel-load serial-out Shift Register that shifts the data in the direction of QA toward QH when clocked. parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load SH/LD\\ input. These registers also feature gated clock CLK inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with SH/LD\ high enables the other clock input. clock inhibit CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited as long as SH/LD\ is high. Data at the parallel inputs are loaded directly into the register.

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Complementary outputs

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Direct overriding load data inputs

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Gated clock inputs

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Parallel-to-serial data conversion