CDCLVD2102

低抖动双路 1:2 通用 LVDS 缓冲器

The clock buffer distributes two clock inputs IN0, IN1 to a total of 4 pairs of differential LVDS clock outputs OUT0, OUT3. Each buffer block consists of one input and 2 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2102 is specifically designed for driving 50- transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage VAC_REF should be applied to the unused negative input pin.

Using the control pin EN, outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled static logical "0", if switched to a logical "1", one buffer with two outputs is disabled and another buffer with two outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C ambient temperature. The CDCLVD2102 is packaged in small 16-pin, 3-mm × 3-mm QFN package.

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Dual 1:2 Differential Buffer

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Low Additive Jitter <300 fs RMS in 10-kHz to 20-MHz

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Low Within Bank Output Skew of 15 ps Max

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Universal Inputs Accept LVDS, LVPECL, LVCMOS

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One Input Dedicated for Two Outputs

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Total of 4 LVDS Outputs, ANSI EIA/ A-644A Standard Compatible

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Clock Frequency up to 800 MHz

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2.375–2.625V Device Power Supply

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LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs

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Industrial Temperature Range –40°C to 85°C

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Packaged in 3mm × 3mm 16-Pin QFN RGT

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ESD Protection Exceeds 3 kV HBM, 1 kV CDM

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APPLICATIONS

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Telecommunications/Networking

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Medical Imaging

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Test and Measurement Equipment

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Wireless Communications

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General Purpose Clocking