MC100LVEL51

差分时钟D触发器 Differential Clock D Flip-Flop

The is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applications which require the ultimate in AC performance at 3.3V VThe reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the LVEL51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to V and the CLKbar input will be biased at V

Features

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475ps Propagation Delay

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2.8GHz Toggle Frequency

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ESD Protection: >4 KV HBM, >200 V MM

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The 100 Series Contains Temperature Compensation

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PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V

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NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -3.8 V

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Internal Input Pulldown Resistors

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Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

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Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

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Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34

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Transistor Count = 114 devices

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Pb-Free Packages are Available