SN74LVTH125DBR

3.3 -V ABT翻两番总线缓冲器，三态输出 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

The is a quadruple Bus Buffer designed specifically for low-voltage 3.3V VCC operation, but with the capability to provide a TTL interface to a 5V system environment. It features independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable OE\ input is high. Active bus-hold circuitry holds unused or un-driven inputs at a valid logic state. Use of pull-up/pull-down resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5V, OE\ should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Supports mixed-mode signal operation

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IOFF and power-up 3-state support hot insertion

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Bus hold on data inputs eliminates the need for external pull-up/pull-down resistors

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Latch-up performance exceeds 500mA per JESD 17

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<0.8V at VCC = 3.3V, TA = 25°C VOLP output ground bounce

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Green product and no Sb/Br