74AUP1G74DC,125

NXP  74AUP1G74DC,125  触发器, 互补输出, 正沿, D, 315 MHz, 20 mA, VSSOP, 8 引脚

The 74AUP1G74DC is a positive-edge trigger D-type Flip-flop with set and reset. It comes with an individual data D, clock, set S\D and reset R\D inputs and complementary Q and Q\ outputs. The S\D and R\D are asynchronous active low inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the low-to-high transition of the clock pulse. The D input must be stable one set-up time prior to the low-to-high clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 to 3.6V. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 to 3.6V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

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High noise immunity

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IOFF Circuitry provides partial power-down mode operation

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Latch-up performance exceeds 100mA per JESD 78, class II

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Low noise overshoot and undershoot <10% of VCC

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0.9µA Maximum low static power consumption