NXP 74HC165D 移位寄存器, HC系列, 并行至串行, 1元件, SOIC, 16 引脚, 2 V, 6 V
The is a 8bit parallel in/serial out shift register with complementary serial outputs in 16 pin SOIC package. This high speed Si-gate CMOS device comply with JEDEC JEDSD 7A. The 74HC165D is pin compatible with low power schottky TTL LSTTL. When parallel load input is LOW, parallel data from the D0 to D7 inputs are loaded into register asynchronously. When parallel load input is high, data enters the register serially at DS input and shifts one place to the right with each positive going clock transition. This feature allows parallel to serial converter expansion by tying Q7 output to DS input of succeeding stage. The clock input is a gated OR structure which allows one input to be used as an active low clock enable input. The low to high transition of clock enable input should only take place while clock input is high for predictable operation.