MC10E154

5位2： 1的MUX -LATCH 5-BIT 2:1 MUX-LATCH

The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2 or both latches the outputs. The Master Reset MR overrides all other controls to set the Q outputs LOW.The 100 series contains temperature compensation.

Features

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850ps Max. LEN to Output

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825ps Max. D to Output

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Differential Outputs

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Asynchronous Master Reset

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Dual Latch-Enables

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PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V

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NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V

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Internal Input Pulldown Resistors

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ESD Protection: > 2 kV HBM, > 200 V MM

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Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

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Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

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Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34

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Transistor Count = 237 devices

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Pb-Free Packages are Available