MC100LVEP34

2.5V / 3.3V ECL / 2 / 4 / 8时钟发生器芯片 2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip

The is a low skew DIV2, DIV4, DIV8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The V pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. V may also rebias AC coupled inputs. When used, decouple V via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VThe common enable ENbar is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input.Upon startup, the internal flip-flops will attain a random state; the master reset MR input allows for the synchronization of the internal dividers, as well as multiple LVEP34s in a system. Single-ended CLK input operation is limited to a V

Features

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35 ps Output-to-Output Skew

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Synchronous Enable/Disable

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Master Reset for Synchronization

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The 100 Series Contains Temperature Compensation.

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PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V

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NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V

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Open Input Default State

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LVDS Input Compatible