SRAM Chip Sync Single 2.5V/3.3V 9M-Bit 256K x 32 7.5ns/3.8ns 100Pin TQFP Tray
* IEEE 1149.1 JTAG-compatible Boundary Scan * 2.5 V or 3.3 V +10%/–10% core power supply * 2.5 V or 3.3 V I/O supply * LBO pin for Linear or Interleaved Burst mode * Internal input resistors on mode pins allow floating mode pins * Byte Write BW and/or Global Write GW operation * Internal self-timed write cycle * Automatic power-down for portable applications * JEDEC-standard 100-lead TQFP and 165-bump BGA packages * 4th Generation, Green TQFP
安富利:
SRAM Chip Sync Single 2.5V/3.3V 9M-Bit 256K x 32 7.5ns/3.8ns 100-Pin TQFP Tray
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