`timescale 1ns/1ps module wallace(Clk,Rst_n,a,b,p); input Clk,Rst_n; input [7:0] a; input [7:0] b; output reg [15:0] p; wire s0,c0,s1,c1,s21,c21,s22,c22,s31,c31,s32,c32,s33,c33,s41,c41,s42,c42,s43,c43,s44,c44,s51,c51,s52,c52,s53,c53,s54,c54,s55,c55; wire s61,c61,s62,c62,s63,c63,s64,c64,s65,c65,s66,c66; wire s71,c71,s72,c72,s73,c73,s74,c74,s75,c75,s76,c76,s77,c77; wire s81,c81,s82,c82,s83,c83,s84,c84,s85,c85,s86,c86,s87,c87; wire s91,c91,s92,c92,s93,c93,s94,c94,s95,c95,s96,c96; wire s101,c101,s102,c102,s103,c103,s104,c104,s105,c105; wire s111,c111,s112,c112,s113,c113,s114,c114; wire s121,c121,s122,c122,s123,c123,s131,c131,s132,c132,s141,c141; adder add0(a[0]&b[0],1'b0,1'b0,s0,c0); adder add1(a[0]&b[1],a[1]&b[0],1'b0,s1,c1); adder add21(a[2]&b[0],a[1]&b[1],a[0]&b[2],s21,c21); adder add22(s21,c1,1'b0,s22,c22); adder add31(a[3]&b[0],a[2]&b[1],a[1]&b[2],s31,c31); adder add32(s31,a[0]&b[3],c21,s32,c32); adder add33(s32,c22,1'b0,s33,c33); adder add41(a[4]&b[0],a[3]&b[1],a[2]&b[2],s41,c41); adder add42(a[1]&b[3],a[0]&b[4],1'b0,s42,c42); adder add43(c31,c32,c33,s43,c43); adder add44(s41,s42,s43,s44,c44); adder add51(a[5]&b[0],a[4]&b[1],a[3]&b[2],s51,c51); adder add52(a[2]&b[3],a[1]&b[4],a[0]&b[5],s52,c52); adder add53(s51,s52,c41,s53,c53); adder add54(c42,c43,c44,s54,c54); adder add55(s53,s54,1'b0,s55,c55); adder add61(a[6]&b[0],a[5]&b[1],a[4]&b[2],s61,c61); adder add62(a[3]&b[3],a[2]&b[4],a[1]&b[5],s62,c62); adder add63(a[0]&b[6],c51,c52,s63,c63); adder add64(c55,c53,c54,s64,c64); adder add65(s61,s62,s63,s65,c65); adder add66(s64,s65,1'b0,s66,c66); adder add71(a[7]&b[0],a[6]&b[1],a[5]&b[2],s71,c71); adder add72(a[4]&b[3],a[3]&b[4],a[2]&b[5],s72,c72); adder add73(a[1]&b[6],a[0]&b[7],c61,s73,c73); adder add74(c62,c63,c64,s74,c74); adder add75(s71,c65,c66,s75,c75); adder add76(s72,s73,s74,s76,c76); adder add77(s75,s76,1'b0,s77,c77); adder add81(a[7]&b[1],a[6]&b[2],a[5]&b[3],s81,c81); adder add82(a[4]&b[4],a[3]&b[5],a[2]&b[6],s82,c82); adder add83(a[1]&b[7],c71,c72,s83,c83); adder add84(c73,c74,c75,s84,c84); adder add85(c76,c77,s81,s85,c85); adder add86(s82,s83,s84,s86,c86); adder add87(s85,s86,1'b0,s87,c87); adder add91(a[7]&b[2],a[6]&b[3],a[5]&b[4],s91,c91); adder add92(a[4]&b[5],a[3]&b[6],a[2]&b[7],s92,c92); adder add93(c81,c82,c83,s93,c93); adder add94(c84,c85,c86,s94,c94); adder add95(c87,s91,s92,s95,c95); adder add96(s93,s94,s95,s96,c96); adder add101(a[7]&b[3],a[6]&b[4],a[5]&b[5],s101,c101); adder add102(a[4]&b[6],a[3]&b[7],c91,s102,c102); adder add103(c92,c93,c94,s103,c103); adder add104(c95,c96,s101,s104,c104); adder add105(s102,s103,s104,s105,c105); adder add111(a[7]&b[4],a[6]&b[5],a[5]&b[6],s111,c111); adder add112(a[4]&b[7],c101,c102,s112,c112); adder add113(c103,c104,c105,s113,c113); adder add114(s111,s112,s113,s114,c114); adder add121(a[7]&b[5],a[6]&b[6],a[5]&b[7],s121,c121); adder add122(c111,c112,c113,s122,c122); adder add123(c114,s121,s122,s123,c123); adder add131(a[7]&b[6],a[6]&b[7],c121,s131,c131); adder add132(c122,c123,s131,s132,c132); adder add141(a[7]&b[7],c131,c132,s141,c141); always@(posedge Clk,negedge Rst_n ) begin if(~Rst_n) p <= 0; else p <= {c141,s141,s132,s123,s114,s105,s96,s87,s77,s66,s55,s44,s33,s22,s1,s0}; end endmodule