MC100EPT24

时钟管理设计采用低偏移和低抖动设备 Clock Management Design Using Low Skew and Low Jitter Devices

The is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a -3.3V, +3.3V and ground are required. The small outline 8-lead SOIC package and the single gate of the EPT24 makes it ideal for those applications where space, performance, and low power are at a premium.

Features

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350ps Typical Propagation Delay

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Maximum Frequency > 1.0GHz

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The 100 Series Contains Temperature Compensation

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Operating Range: VCC= 3.0 V to 3.6 V; VEE= -3.6 V to -3.0 V; GND = 0 V

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PNP LVTTL Inputs for Minimal Loading

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Q Output will default HIGH with inputs open

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Pb-Free Packages are Available