MC10EP451

3.3V / 5VECL 6位差分寄存器与主复位 3.3V / 5VECL 6-Bit Differential Register with Master Reset

The MC10/100EP451 is a 6-bit fully differential register with common clock and single ended Master Reset MR. It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75k-ohm pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < V + 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip-flop is edge triggered, the output reaches a determined, but not predicted, valid state. The positive transition of CLK pin 4 will latch the registers. Master Reset MR HIGH will asynchronously reset all registers forcing Q outputs to go LOW.The 100 Series contains temperature compensation.

Features

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450 ps Typical Propagation Delay

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Maximum Frequency > 3.0 GHz Typical

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Asynchronous Master Reset

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20 ps Skew Within Device, 35 ps Skew Device-To-Device

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PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

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NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V

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Open Input Default State

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Safety Clamp on Inputs

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Pb-Free Packages are Available